This invention relates to integrated circuit structures (i.e., devices), particularly capacitor structures used in random access memory devices on integrated. circuits.
Capacitors are the basic energy storage devices in random access memory devices, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and ferroelectric random access memory (FeRAM) devices. Capacitors store electric charge; a charged capacitor is represented by a 1 and a discharged capacitor by a 0. They consist of two conductors, such as parallel metal or polysilicon plates, which act as the electrodes (i.e., the storage node electrode and the cell plate capacitor electrode), insulated from each other by a dielectric material.
As memory devices increase in memory cell (i.e., storage cell or storage node) density, it is necessary to decrease the size of circuit components, such as capacitors. Thus, there is a continuing challenge to maintain sufficiently high storage capacitance while decreasing cell area. It is desirable that each capacitor possess as much capacitance as possible. Preferably, they should possess at least about 20xc3x9710xe2x88x9215 farads, and more preferably, at least about 60xc3x9710xe2x88x9215 farads, of charge storage capacity. If a capacitor exhibits too little capacitance, it will lose charge placed upon it too rapidly, thereby causing errors in data storage.
The capacitance of a capacitor is dependent upon the dielectric constant of the material placed between the plates of the capacitor, the distance between the plates, and the effective area of the plates. One way to retain (or even increase) the storage capacity of a random access memory device and decrease its size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. For example, in order to achieve the charge storage efficiency in 256 megabit (Mb) memories and above, materials having a high dielectric constant, typically greater than about 10, can be used as the dielectric layer between the two electrodes. The dielectric constant is a value characteristic of a material and is proportional to the amount of charge that can be stored in the material when it is interposed between two electrodes. It is the ratio of the capacitance of a capacitor filled with a given dielectric material to that of the same capacitor having only a vacuum as the dielectric.
Examples of high dielectric constant materials are metal oxides such as TiO2, WO2, Ta2O4, Ta2O5, and Al2O3. These materials have dielectric constants above 10. Metal oxides and metal salts such as BaxSr(1xe2x88x92x)TiO3 [BST], BaTiO3, SrTiO3, PbTiO3, Pb(Zr,Ti)O3 [PZT], (Pb,La)(Zr,Ti)O3 [PLZT], (Pb,La)TiO3 [PLT], KNO3, and LiNbO3 have even higher dielectric constants. These materials have dielectric constants above 50. By comparison, Si3N4 and SiO2/Si3N4 composite films, which are often used in 256 kilobits (Kb) to 64 megabits (Mb) generations of DRAMs, have dielectric constant values of 7 or less.
Unfortunately, high dielectric constant materials are generally incompatible with existing chip manufacturing processes and cannot be simply deposited on a polysilicon electrode as is the case for the lower dielectric constant materials, such as Si3N4 and SiO2/Si3N4 composite layers. For example, these high dielectric materials often form pinholes upon deposition. This incompatibility is believed to be a result of the oxygen rich atmosphere present during the deposition and/or during annealing steps. The O2 oxidizes portions of the materials used for the storage node plate. Also, the capacitors employing standard storage node plate materials undergo physical degradation during thermal cycles due to the diffusion of the cell plate material into the dielectric material.
One means by which these problems can be overcome, at least in part, is through the use of a storage node electrode that consists of a layer of nonoxidizing conductive material such as platinum overlying a barrier layer made of tantalum or titanium nitride, for example, which overlies a conductive plug such as a polysilicon plug. See, U.S. Pat. No. 5,392,189 (Fazan et al.). Although this is an effective technique, other techniques. are needed that allow for the effective use of high dielectric materials in integrated circuits.
The present invention is directed to capacitors, particularly to thin film capacitors used in integrated circuits. These capacitors include a first electrode (i.e., also referred to herein as an electrode plate), a second electrode, and a dielectric material and an organic isolation matrix forming at least one layer between the first and second electrodes. The organic isolation matrix can be formed from a variety of organic materials, such as a soluble polymer, a two-dimensional polymer, or a fullerene. The isolation matrix can be in the form of layers on either side of a layer of the dielectric material, or it can completely surround and encapsulate the dielectric material. In either situation, the dielectric material and organic isolation matrix together preferably form a film of less than about 1000 xc3x85.
The present invention also provides a method of preparing a capacitor comprising: depositing a first material to form a first electrode; depositing a dielectric material and an organic isolation matrix on the first electrode; and depositing a second material to form a second electrode such that the dielectric material and the organic isolation matrix form at least one layer between the first and second electrodes and the organic isolation matrix isolates the dielectric material from the first and second electrodes.
Although the present invention is primarily directed to capacitors, the organic isolation matrix can also be used to isolate any dielectric material used in an integrated circuit. For example, the dielectric material can be the gate dielectric of a field effect transistor device. Thus, the present invention provides an integrated circuit device comprising a dielectric material and an organic isolation matrix in contact with the dielectric material, as well as a method of preparing such an integrated circuit device. The method includes a step of depositing a dielectric material and an organic isolation matrix in contact with the dielectric material such that the dielectric material is isolated by the organic isolation matrix.